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LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain
FEATURES
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DESCRIPTIO
Output IP3 at 100MHz: 47dBm Maximum Output Power: 21dBm Bandwidth: LF to 850MHz Propagation Delay: 0.8ns Maximum Gain: 33dB Noise Figure: 7.3dB (Max Gain) Gain Control Range: 22.5dB Gain Control Step: 1.5dB Gain Control Settling Time: 500ns Output Noise Floor: -134dBm/Hz (Max Gain) Reverse Isolation: -80dB Single Supply: 4.75V to 5.25V Low Power Mode Shutdown Mode Enable/Disable Time: 1s Differential I/O Interface 20-Lead TSSOP Package
The LT(R)5514 is a programmable gain amplifier (PGA) with bandwidth extending from low frequency (LF) to 850MHz. It consists of a digitally controlled variable attenuator, followed by a high linearity amplifier. The amplifier is configured with two identical transconductance amplifiers, hard wired in parallel with individual dedicated enable pins. When both amplifiers are enabled (Standard mode), the LT5514 offers an OIP3 of +47dBm (at 100MHz). Power dissipation can be reduced when a single amplifier is enabled (Low Power mode). Four parallel digital inputs control the gain over a 22.5dB range with 1.5dB step resolution. An on-chip power supply regulator/filter helps isolate the amplifier signal path from external noise sources. The LT5514's open-loop architecture offers stable operation for any practical load conditions, including peakingfree AC response when driving capacitive loads, and excellent reverse isolation. The LT5514 may be operated broadband, where the output differential RC time constant sets the bandwidth, or it may be used as a narrowband driver with the appropriate output filter.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
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High Linearity ADC Driver IF Sampling Receivers VGA IF Power Amplifier 50 Driver Instrumentation Applications
TYPICAL APPLICATIO
56
5V
53
CHOKE 0.1F RF INPUT LO IF BPF IF AMP 0.1F 4 LINES
CHOKE 0.1F
OIP3 (dBm)
50 ROUT = 200 47 ROUT = 100 44 41 38 35 0 50 100 FREQUENCY (MHz) 150 200
5514 TA02
LT5514
100 0.1F GAIN CONTROL
ADC
5514 TA01
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Output IP3 vs Frequency (Standard Mode)
5514f
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1
LT5514
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW ENA 1 VCC1 2 GND 3 GND 4 IN
+
Power Supply Voltage (VCC1, VCC2) .......................... 6V Output Supply Voltage (OUT+, OUT-) ....................... 8V Control Input Voltage (ENA, ENB, PGAx) .. -0.5V to VCC Signal Input Voltage (IN+, IN-) ................... -0.5V to 3V Operating Ambient Temperature Range .. - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
20 ENB 19 VCC2 18 GND 17 GND 21 16 OUT - 15 OUT + 14 GND 13 GND 12 PGA3 11 PGA2
ORDER PART NUMBER LT5514EFE
5 6
IN -
GND 7 GND 8 PGA0 9 PGA1 10
FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150C, JA = 38C/W EXPOSED PAD (PIN 21) IS GND MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ODES OF OPERATIO
MODES Full Power (Standard) Low Power A Low Power B Shutdown ENA High High Low Low
1 2 3 4
ENB High Low High Low
AMP A On On Off Off
AMP B On Off On Off
LT5514 STATE Enable Amp A and Amp B Enable Amp A Enable Amp B Sleep, All Amps Disabled
PROGRA
ABLE GAI SETTI GS
PGA0 High Low High Low High Low High Low High Low High Low High Low High Low PGA1 High High Low Low High High Low Low High High Low Low High High Low Low PGA2 High High High High Low Low Low Low High High High High Low Low Low Low PGA3 High High High High High High High High Low Low Low Low Low Low Low Low POWER GAIN STANDARD MODE* LOW POWER MODE** 33.0dB 30.0dB 31.5dB 28.5dB 30.0dB 27.0dB 28.5dB 25.5dB 27.0dB 24.0dB 25.5dB 22.5dB 24.0dB 21.0dB 22.5dB 19.5dB 21.0dB 18.0dB 19.5dB 16.5dB 18.0dB 15.0dB 16.5dB 13.5dB 15.0dB 12.0dB 13.5dB 10.5dB 12.0dB 9.0dB 10.5dB (Note 3) 7.5dB (Note 3)
5514f
ATTENUATION STEP RELATIVE TO MAX GAIN 1 0dB 2 -1.5dB 3 -3.0dB 4 -4.5dB 5 -6.0dB 6 -7.5dB 7 -9.0dB 8 -10.5dB 9 -12.0dB 10 -13.5dB 11 -15.0dB 12 -16.5dB 13 -18.0dB 14 -19.5dB 15 -21.0dB 16 -22.5dB *ROUT = 200 **ROUT = 400
2
U
W
U
U
U
U
U
WW
WW
W
W
LT5514
DC ELECTRICAL CHARACTERISTICS VCC = 5V, VCCO = 5V, ENA = ENB = 3V, TA = 25C, unless otherwise
noted. (Note 7) (Test circuits shown in Figures 9 and 10)
PARAMETER Supply Voltage (Pins 2, 19) OUT+, OUT- Output Pin DC Common Mode Voltage OUT+, OUT- Pin Instantaneous Voltage with Respect to GND IN+, IN- Bias Voltage PGAO, PGA1, PGA2, PGA3 Input Current PGAO, PGA1, PGA2, PGA3 Input Current OUT+, OUT- Current VCC Supply Current ENA, ENB and PGAx Input Low Voltage ENA, ENB and PGAx Input High Voltage PGAO, PGA1, PGA2, PGA3 Input Current PGAO, PGA1, PGA2, PGA3 Input Current ENA, ENB Input Current ENA, ENB Input Current SYMBOL VCC VCCO VOUT CONDITIONS (Note 4) OUT+, OUT- Connected to VOSUP via Choke Inductors or Resistors (Note 5) Min/Max Limits Apply MIN 4.75 3 2 TYP 5 5 MAX 5.25 6 8 UNITS V V V Normal Operating Conditions
Shutdown DC Characteristics, ENA = ENB = 0.6V VIN(BIAS) IIL(PGA) IIH(PGA) IOUT ICC VIL VIH IIL(PGA) IIH(PGA) IIL(EN) IIH(EN) Max Gain (Note 6) VIN = 0.6V VIN = 5V All Gain Settings All Gain Settings (Note 4) x = 0, 1, 2, 3 x = 0, 1, 2, 3 VIN = 0.6V VIN = 3V and 5V VIN = 0.6V VIN = 3V VIN = 5V Max Gain (Note 6) All Gain Settings (DC) Max Gain All Gain Settings, VOUT = 5V All Gain Settings, IN+, IN- Open Max Gain (Note 4) Min Gain (Note 4) ICC + 2 * IOUT (Max Gain) Max Gain (Note 6) All Gain Settings (DC) Max Gain All Gain Settings, VOUT = 5V All Gain Settings, IN+, IN- Open Max Gain (Note 4) Min Gain (Note 4) ICC + 2 * IOUT (Max Gain) 17 1.34 33 1.34 15 4 18 38 1.49 108 0.3 40 200 64 68 148 1.48 122 0.15 20 100 34 36 76 40 43 91 24 75 80 174 1.65 47 3 20 30 20 100 1.65 44 1.15 1.3 1.5 20 20 20 100 0.6 V A A A A V V A A A A A V S mA A mA mA mA V S mA A mA mA mA
Enable and PGA Inputs DC Characteristics
Standard Mode DC Characteristics, ENA = ENB = 3V VIN(BIAS) RIN gm IOUT ICC ICC(TOTAL) VIN(BIAS) RIN gm IOUT ICC ICC(TOTAL) IN+, IN- Bias Voltage Input Differential Resistance Amplifier Transconductance OUT+, OUT- Quiescent Current VCC1 + VCC2 Supply Current Total Supply Current IN+, IN- Bias Voltage Input Differential Resistance Amplifier Transconductance OUT+, OUT- Quiescent Current VCC1 + VCC2 Supply Current Total Supply Current
IOUT(OFFSET) Output Current Mismatch
Low Power Mode DC Characteristics, ENA = O.6V, ENB = 3V or ENA = 3V, ENB = 0.6V
IOUT(OFFSET) Output Current Mismatch
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LT5514
AC ELECTRICAL CHARACTERISTICS (Standard Mode)
SYMBOL BW PARAMETER Large-Signal -3dB Bandwidth CONDITIONS Dynamic Performance
VCC = 5V, VCCO = 5V, ENA = ENB = 3V, TA = 25C, ROUT = 200. Maximum gain specifications are with respect to differential inputs and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10)
MIN TYP MAX UNITS
All Gain Settings (Note 8) ROUT = 100 ROUT = 200; L1, L2 = 33nH (Figure 9) All Gain Settings, Single Tone, ROUT = 150 fIN = 100MHz (Note 10) Max Gain, fIN = 100MHz PGA1 = Low, fIN = 100MHz fIN = 100MHz (Note 9) fIN = 400MHz (Note 9) All Gain Settings, 10% to 90%, ROUT = 100 All Gain Settings, ROUT = 100 30MHz to 300MHz Frequency Range, ROUT = 100
LF to 850 LF to 500 21 0.30 0.21 -92 -78 500 800 50 500 600
MHz MHz dBm S S dB dB ps ps ps ns ns
POUT(MAX) Clipping Limited Maximum Sinusoidal Output Power gm S12 tr, tf Amplifier Transconductance Reverse Isolation Step Response Rise and Fall Time Group Delay Group Delay Variation PGA Settling Time Enable/Disable Time Distortion and Noise OIP3 Output Third Order Intercept Point for PGA0 = High (PGA1, PGA2, PGA3 Any State) Output Third Order Intercept Point for PGA0 = Low (PGA1, PGA2, PGA3 Any State) HD2 HD3 NFLOOR NF Second Harmonic Distortion Third Harmonic Distortion Output Noise Floor (PGAO, PGA2, PGA3 Any State) Noise Figure
POUT = 9dBm (Each Tone), 200kHz Tone Spacing fIN = 100MHz fIN = 200MHz POUT = 9dBm (Each Tone), 200kHz Tone Spacing fIN = 100MHz fIN = 200MHz POUT = 11dBm (Single Tone), fIN = 50MHz POUT = 11dBm (Single Tone), fIN = 50MHz PGA1 = High, fIN = 100MHz PGA1 = Low, fIN = 100MHz Max Gain, fIN = 100MHz -3dB Step, fIN = 100MHz fIN = 20MHz and 200MHz fIN = 20MHz and 200MHz fIN = 20MHz and 200MHz fIN = 20MHz and 200MHz fIN = 100MHz fIN = 100MHz fIN = 100MHz fIN = 100MHz 1.05
+47.0 +40.5 +42.0 +37.5 -82 -72 -134 -136 7.4 7.7 33 10.5 1.5 0.1 108 2.8 3.4 1.9 1.95
dBm dBm dBm dBm dBc dBc dBm/Hz dBm/Hz dB dB dB dB dB dB pF k pF
Amplifier Power Gain and Gain Step GMAX GMIN GSTEP Maximum Gain Minimum Gain Gain Step Size Gain Step Accuracy RIN CIN RO CO Input Resistance Input Capacitance Output Resistance Output Capacitance
Amplifier I/O Impedance (Parallel Values Specified Differentially)
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LT5514
AC ELECTRICAL CHARACTERISTICS (Low Power Mode)
SYMBOL BW PARAMETER Large-Signal -3dB Bandwidth CONDITIONS All Gain Settings (Note 8), ROUT = 100 All Gain Settings, Single Tone, fIN = 100MHz (Note 10) Max Gain, fIN = 100MHz fIN = 100MHz (Note 9) Dynamic Performance
VCC = 5V, VCCO = 5V, ENA = 3V, ENB = 0.6V, TA = 25C, ROUT = 200. Maximum gain specifications are with respect to differential inputs and differential outputs, unless otherwise noted. (Note 7) (Test circuits shown in Figures 9 and 10)
MIN TYP MAX UNITS
LF to 540 16 0.15 -92
MHz dBm S dB
POUT(MAX) Clipping Limited Maximum Sinusoidal Output Power gm S12 OIP3 Amplifier Transconductance Reverse Isolation Output Third Order Intercept Point for PGA0 = High (PGA1, PGA2, PGA3 Any State) Output Third Order Intercept Point for PGA0 = Low (PGA1, PGA2, PGA3 Any State) HD2 HD3 NFLOOR NF GMAX GMIN GSTEP Second Harmonic Distortion Third Harmonic Distortion Output Noise Floor (PGAO, PGA2, PGA3 Any State) Noise Figure Maximum Gain Minimum Gain Gain Step Size Gain Step Accuracy Amplifier I/O Impedance RIN CIN RO CO Input Resistance Input Capacitance Output Resistance Output Capacitance
Distortion and Noise POUT = 4dBm (Each Tone), 200kHz Tone Spacing, fIN = 100MHz POUT = 4dBm (Each Tone), 200kHz Tone Spacing, fIN = 100MHz POUT = 5dBm (Single Tone), fIN = 50MHz POUT = 5dBm (Single Tone), fIN = 50MHz PGA1 = High, fIN = 100MHz PGA1 = Low, fIN = 100MHz Max Gain Setting, fIN = 100MHz fIN = 20MHz and 200MHz fIN = 20MHz and 200MHz fIN = 20MHz and 200MHz fIN = 20MHz and 200MHz fIN = 100MHz, Parallel Values Specified Differentially fIN = 100MHz, Parallel Values Specified Differentially fIN = 100MHz, Parallel Values Specified Differentially fIN = 100MHz, Parallel Values Specified Differentially 1.05 +40 +36 -76 -72 -138 -140 8.6 27 4.5 1.5 0.1 122 2 5 1.7 1.95 dBm dBm dBc dBc dBm/Hz dBm/Hz dB dB dB dB dB pF k pF
Amplifier Power Gain and Gain Step
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to ground. Note 3: Default state for open PGA inputs. Note 4: VCC1 and VCC2 (Pins 2 and 19) are internally connected. Note 5: External VOSUP is adjusted such that VCCO output pin common mode voltage is as specified when resistors are used. For choke inductors or transformer, VOSUP = VCCO = 5V typ. Note 6: Internally generated common mode input bias voltage requires capacitive or transformer coupling to the signal source.
Note 7: Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Gain always refers to power gain. Input matching is assumed. PIN is the available input power. POUT is the power into the external load, ROUT, as seen by the LT5514 differential outputs. All dBm figures are with respect to 50. Note 8: High frequency operation is limited by the RC time constants at the input and output ports. The low frequency (LF) roll-off is set by I/O interface choice. Note 9: Limited by package and board isolation. Note 10: See "Clipping Free Operation" in the Applications Information section. Refer to Figure 7.
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LT5514
(Standard Mode) TA = 25C, VCC = 5V, VCCO = 5V, ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9) Max Gain Frequency Response with COUT as Parameter, ROUT = 200
36 33 30 27 POWER GAIN (dB) 24 21 18 15 12 9 6 3 10 100 FREQUENCY (MHz) 1000
5514 G02
TYPICAL PERFOR A CE CHARACTERISTICS
Frequency Response for All Gain Steps, ROUT = 100
33 30 27 24 POWER GAIN (dB) POWER GAIN (dB) 21 18 15 12 9 6 3 0 10 100 FREQUENCY (MHz) 1000
5514 G01
Frequency Response at 3dB Attenuation Step with COUT as Parameter, ROUT = 200
36 33 30 27
0.8 0.6 0.4
GAIN ERROR (dB)
POWER GAIN (dB)
24 21 18 15 12 9 6 3 0 10 100 FREQUENCY (MHz) 1000
5514 G04
0.2 0 -0.2 -0.4 -0.6 -0.8 0 3 12 15 6 9 18 ATTENUATION STEP (dB) 21
1544 G05
GAIN ERROR (dB)
COUT = OPEN COUT = 2.2pF COUT = 4.7pF COUT = 10pF COUT = 22pF
Maximum Gain vs Frequency, ROUT = 100 and 200
36 25C -40C 85C 13
POWER GAIN (dB)
33
POWER GAIN (dB)
ROUT = 200
POUT (dBm)
30
ROUT = 100
27 10 100 FREQUENCY (MHz) 1000
5514 G07
6
UW
Frequency Response for All Gain Steps, ROUT = 200
36 33 30 27 24 21 18 15 12 9 6 3 0
COUT = OPEN COUT = 2.2pF COUT = 4.7pF COUT = 10pF COUT = 22pF 10 100 FREQUENCY (MHz) 1000
5514 G03
0
Gain Error vs Attenuation at 25MHz, ROUT = 200
25C -40C 85C 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
Gain Error vs Attenuation at 100MHz, ROUT = 200
25C -40C 85C
0
3
12 15 6 9 18 ATTENUATION STEP (dB)
21
1544 G06
Minimum Gain vs Frequency, ROUT = 100 and 200
25C -40C 85C ROUT = 200 10
POUT vs PIN at 50MHz, Max Gain
25 20 15 10 5 0
STANDARD ROUT = 100 STANDARD ROUT = 200 LOW POWER ROUT = 200
ROUT = 100 7
4 10 100 FREQUENCY (MHz) 1000
5514 G08
-5 -31 -28 -25 -22 -19 -16 -13 -10 PIN (dBm)
-7
5514 G09
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LT5514
(Standard Mode) TA = 25C, VCC = 5V, VCCO = 5V, ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9) Harmonic Distortion vs Attenuation Step at POUT = 7dBm, Freq = 50MHz, ROUT = 200
-72 -75 FIGURE 10 TEST CIRCUIT HD3 PGA0 = LOW HD3 PGA0 = HIGH
TYPICAL PERFOR A CE CHARACTERISTICS
Minimum Gain vs VCC at 120MHz, ROUT = 100
7.8 7.6 7.4 -40C
GAIN (dB)
GAIN (dB)
7.2 25C 7.0 6.8 6.6 6.4 4.5 85C
29.8 25C 29.6 29.4 29.2 29.0 4.5 85C
HD (dBc)
4.7
4.9
5.1
VCC (V)
5514 G10
Harmonic Distortion vs Attenuation Step at POUT = 7dBm, Freq = 50MHz, ROUT = 200
-72 -75 -78 HD3 PGA0 = LOW -40 -45 -50 -55 -60
HD (dBc)
HD (dBc)
HD (dBc)
-81 -84 -87 -90 0 3 12 9 15 6 ATTENUATION STEP (dB) 18 21 HD3 PGA0 = HIGH
HD2
Noise Figure vs Frequency
9.0 8.5 8.0 NF (dB) 7.5 7.0 6.5 6.0 0 50 MAX GAIN 3dB ATTENUATION STEP (PGA1 = LOW) 1.5dB ATTENUATION STEP (PGA0 = LOW) NF (dB) FIGURE 10 TEST CIRCUIT
NOISE FLOOR (dBm/Hz)
100 150 200 250 300 350 400 FREQUENCY (MHz)
5514 G16
UW
5.3
5514 G12
Maximum Gain vs VCC at 120MHz, ROUT = 100
30.4 30.2 30.0 -40C
-78 -81
HD2 -84 -87 -90 0 3 12 9 15 6 ATTENUATION STEP (dB) 18 21
5.5
4.7
4.9
5.1
5.3
5.5
5514 G11
VCC (V)
5514 G12
Harmonic Distortion vs POUT at 50MHz, Max Gain, ROUT = 200
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100
Harmonic Distortion vs POUT at 50MHz, Max Gain, ROUT = 100
-65 -70 -75 -80 -85 -90 -95 -100 -3 0 3 9 12 6 POUT (dBm) 15 18 21 HD5 HD4 HD3 HD2
HD3 HD2 HD5 HD4
-5
-2
1
7 10 4 POUT (dBm)
13
16
19
5514 G14
5514 G15
NF vs Attenuation Step at Freq = 100MHz
30 27 24 21 18 15 12 9 6 3 0
-139 -134
Output Noise Floor vs Attenuation Step, Freq = 100MHz, ROUT = 200
-133 FIGURE 10 TEST CIRCUIT
FIGURE 10 TEST CIRCUIT
PGA1 = HIGH -135 -136 PGA1 = LOW -137 -138
0
3
15 6 9 12 18 ATTENUATION STEP (dB)
21
5514 G17
0
3
6 9 12 15 18 ATTENUATION STEP (dB)
21
5514 G18
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LT5514
(Standard Mode) Two tones, 200kHz spacing, TA = 25C, ENA = ENB = 5V, VCC = 5V, VCCO = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 10) OIP3 vs Frequency at PIN = -23dBm Max Gain, ROUT = 200
57 54 51 25C -40C 85C 57 54 51 25C -40C 85C
TYPICAL PERFOR A CE CHARACTERISTICS
OIP3 (dBm)
OIP3 (dBm)
48 45 42 39 36 0 50 100 FREQUENCY (MHz)
5514 G19
48 45 42 39 36
OIP3 (dBm)
150
OIP3 vs Attenuation Step at Freq = 100MHz, PIN = -23dB, ROUT = 200
49 48 47
OIP3 (dBm)
70 60 50
46 45 44 43 42 41 0 3
25C 40 30 20 10 0 4.5 -40C
CURRENT (mA)
CURRENT (A)
3dB ATTENUATION STEP (PGA0 = HIGH)
1.5dB ATTENUATION STEP (PGA0 = LOW)
12 15 6 9 18 ATTENUATION STEP (dB)
Single-Ended Output Current vs Attenuation Step
41 1.60
CURRENT (mA)
40 85C 25C 39 -40C 1.45 VIN(BIAS) (V) 1.50 -40C 25C 85C
38
0
8
UW
21
1544 G22
OIP3 vs Frequency at PIN = -23dBm Max Gain, ROUT = 100
57 54 51
OIP3 vs Frequency at PIN = -23dBm Max Gain and 1.5dB Attenuation Step, ROUT = 200
MAX GAIN 48 45 42 39 36 1.5dB ATTENUATION STEP
200
0
50
100 FREQUENCY (MHz)
150
200
5514 G20
0
50
100 FREQUENCY (MHz)
150
200
5514 G21
ICC Shutdown Current vs VCC, ENA = ENB = 0.6V
160 155 150 145 140
Total ICC vs Attenuation Step
85C
85C 25C
-40C 135 130 4.7 4.9 5.1 5.3 5.5
5514 G23
0
3
INPUT VCC (V)
6 9 12 15 18 ATTENUATION STEP (dB)
21
5514 G24
VIN(BIAS) vs Attenuation Step
1.55
3
6 9 12 15 18 ATTENUATION STEP (dB)
21
5514 G25
1.40
0
3
6 9 12 15 18 ATTENUATION STEP (dB)
21
5514 G26
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LT5514
(Standard Mode) TA = 25C, VCC = 5V, VCCO = 5V, ENA = ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. Test circuit shown in Figure 10 unless otherwise noted. Note 1: Subtract 0.75ns calibration delay from output plots to estimate the LT5514 group delay. Note 2: When specified, COUT is connected differentially across the LT5514 OUT+, OUT- output pins. Pulse Response vs COUT at Max Gain. Output Level is 2VP-P into 50 External Load
0pF COUT 0pF 1pF 1.8pF 3.3pF 4.7pF 6.8pf 10pF 11pF 18pF
TYPICAL PERFOR A CE CHARACTERISTICS
INPUT
22pF TO GROUND EACH OUTPUT
RMATCH = 255 2ns/DIV
5514 G27
Pulse Response vs Attenuation, Output Level is 2VP-P at Max Gain into 50 External Load
RMATCH = 255 MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP
INPUT
Pulse Response vs Attenuation, LT5514 Levels are: VIN = 66mVP-P, VOUT = 2VP-P at Max Gain
ROUT = 100 MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP
INPUT
FIGURE 9 TEST CIRCUIT 1ns/DIV
5514 G32
UW
Pulse Response vs Output Level at Max Gain. Indicated Voltage Levels are into 50 External Load
COUT = 0.82pF 4VP-P 3VP-P 2VP-P INPUTS
Pulse Response vs Attenuation, Output Level is 4VP-P at Max Gain into 50 External Load
INPUT
MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP
2ns/DIV
5514 G28
1ns/DIV
5514 G29
Pulse Response vs Attenuation, Output Level is 2VP-P at Max Gain into 50 External Load
RMATCH = 255, COUT = 1.8pF MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP
INPUT
1ns/DIV
5514 G30
1ns/DIV
5514 G31
Pulse Response vs Attenuation, LT5514 Levels are: VIN = 66mVP-P, VOUT = 4VP-P at Max Gain
ROUT = 200 MAX GAIN 1.5dB STEP 3dB STEP 6dB STEP 12dB STEP
INPUT
FIGURE 9 TEST CIRCUIT 1ns/DIV
5514 G33
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LT5514
(Low Power Mode) TA = 25C, VCC = 5V, VCCO = 5V, ENA = 3V, ENB = 0.6V or ENA = 0.6V, ENB = 3V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 10) OIP3 vs Frequency at Pin = -23dBm, Max Gain and 1.5dB Attenuation Step, ROUT = 200
54 51 48 -40 -45 -50 -55 -60
TYPICAL PERFOR A CE CHARACTERISTICS
OIP3 (dBm)
HD(dBc)
45 MAX GAIN 42 39 36 33 30 0 50 100 FREQUENCY (MHz)
5514 G34
-70 -75 -80 -85 -90 -95
HD3
HD2
NF (dB)
1.5dB ATTENUATION STEP
150
NF vs Attenuation Step at Freq = 100MHz
30 27 24 21
NOISE FLOOR (dBm/Hz)
NF (dB)
18 15 12 9 6 3 0
0
3
15 6 9 12 18 ATTENUATION STEP (dB)
Total ICC vs VCC
80 78 75 73 -40C 70 68 65 19.0 85C 20.5 CURRENT (mA) CURRENT (mA) 21.0
VIN(BIAS) (V)
25C
0
3
6 9 12 15 18 ATTENUATION STEP (dB)
10
UW
21
5514 G37
Harmonic Distortion vs POUT at 50MHz, Max Gain, ROUT = 200
10.0 9.5 9.0 8.5 8.0
HD5 HD4
Noise Figure vs Frequency
1.5dB ATTENUATION STEP (PGA0 = LOW)
-65
MAX GAIN 3dB ATTENUATION STEP (PGA1 = LOW)
7.5 7.0
-100 200 -6 -3 0 6 POUT (dBm) 3 9 12 15
0
50
100 150 200 250 300 350 400 FREQUENCY (MHz)
5514 G36
5514 G35
Output Noise Floor vs Attenuation Step, Freq = 100MHz, ROUT = 200
-136 -137 -138 -139 -140 -141 -142 PGA1 = LOW PGA1 = HIGH
Pulse Response vs Output Level at Max Gain. Indicated Voltage Levels are into 50 External Load
COUT = 0.82pF 2VP-P 1.5VP-P 1VP-P INPUTS
0
3
6 9 12 15 18 ATTENUATION STEP (dB)
21
5514 G38
2ns/DIV
5514 G39
Single-Ended Output Current vs Attenuation Step
1.60
VIN(BIAS) vs Attenuation Step
1.55
20.0
85C 25C
1.50
-40C 25C
19.5 -40C
1.45
85C
21
5514 G40
1.40 0 3 6 9 12 15 18 ATTENUATION STEP (dB) 21
5514 G41
0
3
6 9 12 15 18 ATTENUATION STEP (dB)
21
5514 G42
5514f
LT5514
PI FU CTIO S
ENA (Pin 1): Enable Pin for Amplifier A. When the input voltage is higher than 3V, amplifier A is turned on. When the input voltage is less than or equal to 0.6V, amplifier A is turned off. This pin is internally pulled to ground if not connected. VCC1 (Pin 2): Power Supply. This pin is internally connected to VCC2 (Pin 19). Decoupling capacitors (1000pF and 0.1F for example) may be required in some applications. GND (Pins 3, 4, 7, 8, 13, 14, 17, 18): Ground. IN+ (Pin 5): Positive Signal Input Pin with Internal DC Bias. IN- (Pin 6): Negative Signal Input Pin with Internal DC Bias. PGA0 (Pin 9): Amplifier PGA Control Input Pin for the 1.5dB Attenuation Step (see Programmable Gain table). Input is high when input voltage is greater than 3V. Input is low when input voltage is less than or equal to 0.6V. This pin is internally pulled to ground if not connected. PGA1 (Pin 10): Amplifier PGA Control Input Pin for the 3dB Attenuation Step (see Programmable Gain table). Input is high when input voltage is greater than 3V. Input is low when input voltage is less than or equal to 0.6V. This pin is internally pulled to ground if not connected. PGA2 (Pin 11): Amplifier PGA Control Input Pin for the 6dB Attenuation Step (see Programmable Gain table). Input is high when input voltage is greater than 3V. Input is low when input voltage is less than or equal to 0.6V. This pin is internally pulled to ground if not connected. PGA3 (Pin 12): Amplifier PGA Control Input Pin for 12dB Attenuation Step (see Programmable Gain table). Input is high when input voltage is greater than 3V. Input is low when input voltage is less than or equal to 0.6V. This pin is internally pulled to ground if not connected. OUT+ (Pin 15): Positive Amplifier Output. A transformer with center tap tied to VCC or a choke inductor is recommended to source the DC quiescent current. OUT- (Pin 16): Negative Amplifier Output. A transformer with center tap tied to VCC or a choke inductor is recommended to source the DC quiescent current. VCC2 (Pin 19): Power Supply. This pin is internally connected to VCC1 (Pin 2). ENB (Pin 20): Enable Pin for Amplifier B. When the input voltage is higher than 3V, amplifier B is turned on. When the input voltage is less than or equal to 0.6V, amplifier B is turned off. This pin is internally pulled to ground if not connected. Exposed Pad (Pin 21): Ground. This pin must be soldered to the printed circuit board ground plane for good heat transfer.
BLOCK DIAGRA
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LT5514
5 6
IN+ IN-
ATTENUATOR RIN 100
AMPLIFIER A OUT - OUT+ 16 15
AMPLIFIER B
VOLTAGE REGULATOR AND BIAS GND (3, 4, 7, 8 13, 14, 17, 18) 2
GAIN CONTROL LOGIC
ENABLE CONTROL
VCC1 19
VCC2
PGA3 12 11
PGA2 PGA1 10 9
PGA0
ENB 20 1
ENA 21
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Figure 1. Functional Block Diagram
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LT5514
APPLICATIO S I FOR ATIO
Circuit Operation
The LT5514 is a high linearity amplifier with high impedance output (Figure 1). It consists of the following sections: * An input variable attenuator "gain-control" block with 100 input impedance * Two parallel, differential transconductance amplifiers, each with independent enable inputs * An internal bias block with internal voltage regulator * A gain control logic block The LT5514 amplifier provides amplification with very low distortion using a linearized open-loop architecture. In contrast with high linearity amplifiers employing negative feedback, the LT5514 offers: * Stable operation for any practical load * A capacitive output reactance (not inductive) that provides peaking free AC response to capacitive loads
GAIN (dB)
* Exceptional reverse isolation of -100dB at 50MHz and -78dB at 300MHz (package and board leakage limited) The LT5514 is a transconductance amplifier and its operation can be understood conceptually as consisting of two steps: First, the input signal voltage is converted to an output current. The intermodulation distortion (in dBc) of the LT5514 output current is determined by the input signal level, and is almost independent of the output load conditions. Thus, the LT5514's input IP3 is also nearly independent of the output load. Next, the external output load (ROUT) converts the output current to output voltage (or power). The LT5514's voltage and power gain both increase with increasing ROUT. Accordingly, the output power and output IP3 also improve with increasing ROUT. The actual output linearity performance in the application will thus be set by the choice of output load, as well as by the output network. Maximum Gain Calculation The maximum power gain (with the 0dB attenuation step) is: GPWR(dB) = 10 * log(gm2 * RIN * ROUT)
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where: gm is the LT5514 transconductance = 0.3S in Standard mode (0.15S in Low Power mode). RIN is the LT5514 differential input impedance 108 in Standard mode (122 in Low Power mode). Input impedance matching is assumed. ROUT is the external differential output impedance as seen by the LT5514's differential outputs. ROUT should be distinguished from the actual load impedance, RLOAD, which will typically be coupled to the LT5514 output by an impedance transformation network. The power gain as a function of ROUT is plotted in Figure 2. The ideal curves are straight lines. The curved lines indicate the roll-off due to the finite (noninfinite) output resistance of the LT5514.
45 40 35 30 25 20 15 10 5 0 20 100 ROUT ()
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STANDARD MODE LOW POWER MODE STD WITH RO LP WITH RO 1000 2000
Figure 2. Power Gain as a Function of ROUT
The actual available output power (as well as power gain and OIP3) will be reduced by losses in the output interface, consisting of: * The insertion loss of the output impedance transformation network (for example the transformer insertion loss in Figure 6) * About -3dB loss if a matching resistor (RMATCH in Figure 6) is used to provide output load impedance back-matching (for example when driving transmission lines)
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Input Interface
For the lowest noise and highest linearity, the LT5514 should be driven with a differential input signal. Singleended drive will severely degrade linearity and noise performance. Example input matching networks are shown in Figures 3 and 4. Input matching network design criteria are: * DC block the LT5514 internal bias voltage (see Input Bias Voltage section for DC coupling information) * Match the source impedance to the LT5514, RIN 108 * Provide well balanced differential input drive (capacitor C2 in Figure 4) * Minimize insertion loss to avoid degrading the noise figure (NF)
R1 50 VSRC R2 50 C1 IN C2
+
LT5514
-
RIN 100
IN-
+
LT5514 F03
Figure 3. Input Capacitively-Coupled to a Differential Source
RSRC 50 T1 1:2
IN
+
LT5514
*
VSRC
* *
-
RIN 100
IN- C2 0.33F
+
LT5514 F04
Figure 4. Input Transformer-Coupled to a Single-Ended Source
Output Interface The output interface network provides an impedance transformation between the actual load impedance, RLOAD, and the LT5514 output loading, ROUT, chosen to maximize power or linearity, or to minimize output noise, or for some other criteria as explained in the following sections. Two examples of output matching networks are shown in Figures 5 and 6 (as implemented in the LT5514 demo boards).
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VOSUP C3 IN+ LT5514 R1 51 ROUT R2 51 C1 RLOAD 50 RLOAD 50
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RIN 100 C2
IN-
+
LT5514 F05
Figure 5. Output Impedance-Matched and Capacitively Coupled to a Differential Load
Note: In Figure 5, (choke) inductors may be placed in parallel with or used to replace resistors R1 and R2, thus eliminating the DC voltage drop across these resistors.
VOSUP RMATCH 255 (OPTIONAL) ROUT C1 T2 4:1 RLOAD 50
IN+
LT5514
-
RIN 100
IN-
+
* *
*
LT5514 F06
Figure 6. Output Impedance-Matched and Transformer-Coupled to a Single-Ended Load
Output network design criteria are: * Provide DC isolation between the LT5514 DC output voltage and RLOAD. * Provide a path for the output DC current from the output voltage source VOSUP. * Provide an impedance transformation, if required, between the load impedance, RLOAD, and the optimum ROUT loading. * Set the bandwidth of the output network. * Optional: Provide board output impedance matching using resistor RMATCH (when driving a transmission line). * Use high linearity passive parts to avoid introducing noninearity. Note that there is a noise penalty of up to 6dB when using power delivered by only one output in Figure 5.
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APPLICATIO S I FOR ATIO
Clipping Free Operation
The LT5514 is a class A amplifier. To avoid signal distortion, the user must ensure that the LT5514 outputs do not enter into current or voltage limiting. The following discussion applies to standard mode operation at maximum gain. To avoid current clipping, the output signal current should not exceed the DC quiescent current, IOUT = 40mA (typical). Correspondingly, the maximum input voltage, VIN(MAX), is IOUT/gm = 133mV (peak). In power terms, PIN(MAX) = -10.8dBm (assuming RIN = 108). To avoid output voltage clipping (due to LT5514 output stage saturation or breakdown), the single-ended output voltage swing should stay within the specified limits; i.e., 2V VOUT 8V. For a DC output bias of 5V, the maximum single ended swing will be 3Vpeak and the maximum differential swing will be 6Vpeak. The simultaneous onset of both current and voltage limiting occurs when ROUT = 6Vpeak/40mA =150 (typ) for a maximum POUT = 20.8dBm. This calculation applies for a sinusoidal signal. For nonsinusoidal signals, use the appropriate crest factor to calculate the actual maximum power that avoids output clipping. For nonoptimal ROUT values, the maximum available output power will be lower and can be calculated (considering current limiting for ROUT < 150, and voltage limiting for ROUT > 150). The result of this calculation is shown in Figure 7. The LT5514 input should not be overdriven (PIN > -10dBm). The consequences of overdrive are reduced
25 VCC = VCCO = 5V CURRENT LIMIT VOLTAGE LIMIT
20
POUT(MAX) (dBm)
15
10
5 STANDARD MODE LOW POWER MODE 0 20 100 ROUT ()
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1000 2000
Figure 7. Maximum Output Power as a Function of ROUT
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bandwidth and, when the frequency is greater than 50MHz, reduced output power. Input Bias Voltage The LT5514 IN+, IN- signal inputs are internally biased to 1.48V common mode when enabled, and to 1.26V in shutdown mode. These inputs are typically coupled by means of a capacitor or a transformer to a signal source, and impedance matching is assumed. In shutdown mode, the internal bias can handle up to 1A leakage on the input coupling capacitors. This reduces the turn-on delay due to the input coupling RC time constant when exiting shutdown mode. If DC coupling to the input is required, the external common mode bias should track the LT5514's internal common mode level. The DC current from the LT5514 inputs should not exceed IIN(SINK) = -400A and IIN(SOURCE) = 800A in Standard mode and half of these values in Low Power mode. Stability Considerations The LT5514's open-loop architecture allows it to drive any practical load. Note that LT5514 gain is proportional to the load impedance, and may exceed the reverse isolation at frequencies above 1GHz if the LT5514's outputs are left unloaded, with instability as the undesirable consequence. In such cases, placing a resistive differential load (e.g., 2k) or a small capacitor at the LT5514 outputs can be used to limit the maximum gain. The LT5514 has about 30GHz gain-bandwidth product. Hence, attention must be paid to the printed circuit board layout to avoid output pin to input pin signal coupling (the evaluation board layout is a good example). Due to the LT5514's internal power supply regulator, external supply decoupling capacitors typically are not required. Likewise, decoupling capacitors on the LT5514 control inputs typically are not needed. Note, however, that the Exposed Pad on the LT5514 package must be soldered to a good ground plane on the PCB. PGA Function, Linearity and NF As described in the Circuit Operation section, the LT5514 consists of a variable (step) attenuator followed by a high
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LT5514
APPLICATIO S I FOR ATIO
gain output amplifier. The overall gain of the LT5514 is digitally controlled by means of four gain control pins with internal pull-down. Minimum gain is programmed when the gain control pins are set low or left floating. In shutdown mode, these PGA inputs draw <10A leakage current, regardless of the applied voltage. The 6dB and 12dB attenuation steps (PGA2 and PGA3) are implemented by switching the amplifier inputs to an input attenuator tap. The 3dB attenuation step (PGA1) changes the amplifier transconductance. The output IP3 is approximately independent of the PGA1, PGA2 and PGA3 gain settings. However, the 1.5dB attenuation step utilizes a current steering technique that disables the internal linearity compensation circuit, and the OIP3 can be reduced by as much as 6dB when PGA0 is low. Therefore, to achieve the LT5514's highest linearity performance, the PGA0 pin should be set high. The LT5514 noise figure is 7.3dB in the maximum gain state. For the -3dB attenuation setting, the NF is 7.6dB. The noise figure increases in direct proportion to the amount of programmed gain reduction for the 1.5dB, 6dB and 12dB steps. The output noise floor is proportional to the output load impedance, ROUT. It is almost constant for PGA1 = high and for any PGA0, PGA2, PGA3 state. When PGA1 = low, the output noise floor is 2.7dB lower (see Typical Performance Characteristics). Other Linearity Considerations LT5514 linearity is a strong function of signal frequency. OIP3 decreases about 13dB for every octave of frequency increase above 100MHz. As noted in the Circuit Operation section, at any given frequency and input level, the LT5514 provides a current output with fairly constant intermodulation distortion figure in dBc, regardless of the output load value. For higher ROUT values, more gain and output power is available, and better OIP3 figures can be achieved. However, high ROUT values are not easily implemented in practice, limited by the availability of high ratio output impedance transformation networks. Linearity can also be limited by the output RC time constant (bandwidth limitations), particularly for high ROUT
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values. A solution is outlined in the Bandpass Applications section. The LT5514 linearity degrades when common mode signal is present. The input transformer center tap should be decoupled to ground to provide a balanced input differential signal and to avoid linearity degradation for high attenuation steps. When the signal frequency is lower than 50MHz, and there is significant common mode signal, then high attenuation settings may result in degraded linearity. At signal frequencies below 100MHz, the LT5514's internal linearity compensation circuitry may provide "sweet spots" with very high OIP3, in excess of +60dBm. This almost perfect distortion correction cannot be sustained over the full operating temperature range and with variations of the LT5514 output load (complex impedance ZOUT). Users are advised to rely on data shown in the Typical Performance Characteristics curves to estimate the dependable linearity performance. Wideband Applications At low frequencies, the value of the decoupling capacitors, choke inductors and choice of transformer will set the minimum frequency of operation. Output DC coupling is possible, but this typically reduces the LT5514's output DC bias voltage, and thus the output swing and available power. At high frequencies, the output RC time constants set an upper limit to the maximum frequency of operation in the case of the wideband output networks presented so far. For example the LT5514 output capacitance, COUT = 1.9pF, and a pure resistive load, ROUT = 200, will set the -3dB bandwidth to about 400MHz. In an actual application, the RLOAD * CLOAD product may be even more restrictive. The use of wideband output networks will not only limit the bandwidth, but will also degrade linearity because part of the available power is wasted driving the capacitive load. The LT5514's output reactance is capacitive. Therefore improved AC response is possible by using external series output inductors. When driving purely resistive loads, an inductor in series with the LT5514 output may help to achieve maximally flat AC response as exemplified in the characterization setup schematic (Figure 9).
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APPLICATIO S I FOR ATIO
For example, for ROUT = 200, L1, L2 = 33nH results in 500MHz bandwidth. The series inductor can extend the application bandwidth, but it provides no improvement in linearity performance. Series inductance may also produce peaking in the AC response. This can be the case when (high Q) choke inductors are used in an output interface such as in Figure 5, and the PCB trace (connection) to the load is too long. Since the LT5514's output impedance is relatively high, the PCB trace acts as a series inductor. The most direct solution is to shorten the connection lines by placing the driver closer to the load. Another solution to flatten the AC response is to place resistance close to the LT5514 outputs. In this way the connection line behaves more like a terminated transmission line, and the AC peaking due to the capacitive load can be removed. Bandpass Applications For narrow band IF applications, the LT5514's output capacitance and the application load capacitance can be incorporated as part of an LC impedance transformation network, giving improved linearity performance for signal frequencies greater than 100MHz. Figure 8 is an example of such a network. The network consists of two parallel resonant LC tank circuits critically coupled by capacitors C1 and C2. The ROUT to RLOAD transformation ratio in this particular implementation is 2. The choice of impedance transformation ratio is more flexible than in the wideband case.
ENA ENB
VCC T1 1:2 C8 0.1F IN+ 100 RSRC 50 VSRC TC2-1T C9 0.33F IN- LT5514
-
DUT
+
PGA0 PGA1 PGA2 PGA3
Figure 8. Bandpass Output Transformation Network Example
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The LC network is a bandpass filter, a useful feature in many applications. A variety of bandpass matching network configurations are conceivable, depending on the requirements of the particular application. The design of these networks is facilitated by the fact that the LT5514 outputs are not destabilized by reactive loading. Note that these LC networks may distort the output signal if their amplitude and phase response exhibit nonlinear behavior. For example, if resistors R1 and R2 in Figure 5 are replaced with LC resonant tank circuits, then severe OIP3 degradation may occur (e.g., 4dB to 6dB at 200MHz). Low Output Noise Floor Applications In some applications the maximum output noise floor is specified. The LT5514 output noise floor is elevated above the available noise power (-174dBm/Hz into 50) by the NF + Gain. Consequently, reduction of the LT5514's power gain is the only way to reduce the output noise floor. In fixed gain applications, the LT5514 can be set to 3dB attenuation relative to maximum gain. As shown in the Typical Performance Characteristics, this gives a 2.8dB reduction in the output noise floor with no loss of linearity. In general, the output noise floor can be reduced by decreasing ROUT (and hence power gain), at the cost of reduced OIP3. In some situations, it may be feasible to use two LT5514 parts in parallel. In this case, the effective gm doubles,
NOTE: C3 + CLOAD = 12pF C4 + CLOAD = 12pF L5 56nH L6 C1 56nH 12pF C7 0.1F L3 56nH C3 RLOAD 50 VOSUP ROUT 200 C6 2.2pF C2 12pF C5 5.6pF L4 56nH RLOAD 100 CLOAD C4 GAIN = 33dB OIP3 (LOAD) = +41dBm UP TO 9dBm PER TONE 1dB BANDWIDTH: fL = 130MHz fU = 220MHz
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RLOAD 50
CLOAD
LT5514
APPLICATIO S I FOR ATIO
allowing all impedances to be scaled downward by a factor of two. The NF and power gain remain the same in this case, but the OIP3 increases by 3dB. Then, with a further reduction of ROUT by a factor of two, the gain and output noise floor decrease by 3dB, while yielding the same linearity as for one part. As an added benefit, two LT5514 parts in parallel can drive an ROUT reduced by a factor of four, thus relaxing or eliminating the need in some cases for an output impedance transformation network. Low Power Mode As described in the Circuit Operation section, the LT5514 consists of two parallel gain blocks. These blocks are independently enabled or disabled. "Low Power mode"
VCC C1 0.33F T1 1:1 RSRC 50 VSRC C7 47nF C8 47nF R9 35.7 R10 35.7 R7 35.7 R8 35.7 ATT = 7.7dB C2 0.1F
IN+ IN-
-
DUT ROUT
+
R5 51k R6 51k COUT (OPT)
ETC-11-13
PGA0 PGA1 PGA2 PGA3
Figure 9. Characterization Board (Simplified Schematic)
VCC C2 0.1F IF IN ENA 1 2 3 4 5 6 7 8 9 10 ENA ENB VCC1 VCC2 GND GND LT5514 GND GND IN+ OUT- IN- OUT+ GND GND GND GND PGA0 PGA3 PGA1 PGA2 ENB 20 19 18 17 16 15 14 13 12 11 C4 0.1F T2 4:1 ROUT 100 RMATCH 255 C3 4.7F VOSUP IF OUT
T1 1:2
J1 0
TC2-1T
C1 0.47F
TRANSFORMER DEMO BOARD
PGA0 PGA1
Figure 10. Output Transformer Application Board (Simplified Schematic)
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refers to circuit operation with only a single block enabled. An amplifier in Low Power mode will have the same basic characteristics as in Standard mode (both gain blocks enabled), except that the gm decreases from 0.3S to 0.15S, and the maximum output current is halved. In Low Power mode, the standard LT5514 evaluation board will produce about 6dB less gain, (because the LT5514's gm is reduced, while RIN and ROUT are the same) and 6dB lower OIP3. LT5514 Characterization The LT5514's typical performance data are based on the test circuits shown in Figures 9 and 10. Figure 9 does not necessarily reflect the use of the LT5514 in an actual application. (For that, see the Application Boards section.)
ENA ENB R1 25 COUT (OPT) LT5514 L1 (OPT) L2 (OPT) R3 37.4 R4 37.4 R1 25 C5 47nF C6 47nF C4 0.1F C3 4.7F VOSUP T1 1:1 RLOAD 50 ETC-11-13 ROUT R3, R4 ATT 100 37.4 9dB 200 87.4 12dB
5514 F09
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VCCO MONITOR
* *
*
RLOAD 50 J2 0
TC4-1W
PGA2 PGA3
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LT5514
APPLICATIO S I FOR ATIO
Rather, it represents a compromise that most accurately measures the actual operation of the part by itself, undistorted by the artifacts of the impedance transformation network, or by external bandwidth limiting factors. Balun transformers are used to interface with single-ended test equipment. Input and output resistive attenuators (not shown) provide broadband I/O impedance control. The L1, L2 inductors are selected for maximally flat AC output response. COUT (normally open) shows the placement of capacitive loading when this is specified as a characterization variable. The VCCO monitor pin allows setting the output DC level (5V typical) by adjusting voltage VOSUP. Application (Demo) Boards The LT5514 demo boards are provided in the versions shown in Figure 10 (with output transformer) and Figure 11 (without output transformer). All I/O signal ports are matched to 50. Moreover, 1k resistors (not shown) connect all six control pins (ENA, ENB, PGA0, PGA1, PGA2, PGA3) to VCC, such that the LT5514 is shipped in maximum gain state and with both amplifier blocks enabled (Standard mode). The gain setting can be changed by connecting the control pins to ground. Test points (TP1, TP2, TP3) are provided to monitor the input and output DC bias voltage. Jumper J1 can be removed when differential input is desired, but
OIP3 (dBm)
VCC C2 0.1F
ENA 1 2 3 4 5 6 7 8 9 10 ENA ENB VCC1 VCC2 GND GND LT5514 GND GND IN+ OUT- IN- OUT+ GND GND GND GND PGA0 PGA3 PGA1 PGA2
IF IN
T1 1:2
J1 0
TC2-1T
C1 0.47F
DIFFERENTIAL OUTPUT RESISTIVE DEMO BOARD
PGA0 PGA1
Figure 11. Wideband Differential Output Application Board (Simplified Schematic)
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in that case, T1 should be changed to a 1:1 center-tap transformer to preserve 50 input matching. The demo board is shipped with optional output back-matching resistor RMATCH = 255. This results in a net output load, ROUT = 100, presented to the LT5514. The Output Transformer Application Board (Figure 10) is one example of an output impedance transformation (T2 transformer). For the Typical Performance Characteristics curves, all linearity tests are performed on this board. By removing RMATCH, the performance with ROUT = 200 can be evaluated (provided the lack of impedance back-matching is suitably remedied). Measured OIP3 for both cases, ROUT = 100 and 200, is shown in Figure 12.
58 55 52 49 46 43 40 37 34 0 50 100 FREQUENCY (MHz)
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DUT RMATCH = 255 BOARD RMATCH = 255 DUT RMATCH = OPEN BOARD RMATCH = OPEN
150
200
Figure 12. Typical OIP3 for Transformer Board
ENB VOSUP 20 19 18 17 16 15 14 13 12 11 R1 50 R2 50 C4 0.1F C3 4.7F IF OUT
ROUT 50
C5 47nF
RLOAD 100
C6 47nF
J2 0PEN
PGA2 PGA3
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APPLICATIO S I FOR ATIO
At high frequency, the difference between the top and bottom curves in Figure 12 is simply power loss. Starting from the LT5514 intrinsic performance at ROUT = 200 (top curve), the next lower curve takes into account the transformer insertion loss. The next curve below this shows the LT5514 OIP3 with ROUT = 100. The bottom curve in the plot includes the effects of transformer insertion loss, with ROUT = 100, and the additional effect of loss due to RMATCH. The transformer board can provide a differential output when Jumper J2 is removed.
PACKAGE DESCRIPTIO
FE Package 20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
3.86 (.152)
6.60 0.10 4.50 0.10 SEE NOTE 4
0.45 0.05 1.05 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.25 REF 1 2 3 4 5 6 7 8 9 10
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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The Wideband Differential Output Application Board (Figure 11) is an example of direct coupling (no transformer) to the load, and has wider output bandwidth. This board gives direct access to the LT5514's output pins, and was used for stability tests. Higher VOSUP (7V) is required to compensate for the DC voltage drop on R1 and R2. Use TP2, TP3 to monitor the actual LT5514 output bias voltage. By replacing R1 and R2 with inductors, this board can operate with a 5V supply. However, this may limit the minimum signal frequency. For example, an 820nH choke inductor will limit the lowest signal frequency to 40MHz.
Exposed Pad Variation CB
6.40 - 6.60* (.252 - .260) 3.86 (.152) 20 1918 17 16 15 14 13 12 11 2.74 (.108) 6.40 2.74 (.252) (.108) BSC 1.20 (.047) MAX 0 - 8 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006)
FE20 (CB) TSSOP 0204
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4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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LT/TP 0504 1K * PRINTED IN THE USA
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